Field of the Invention
The invention relates to a non-volatile semiconductor memory device, especially relates to a structure of a memory array having Not AND (NAND) type string memory cell.
Description of Related Art
Flash memory is a memory element that is applied to a wide variety of electronic equipments, such as digital camera, smartphone, etc. In the market, the flash memory is further required to be small in volume and large in capacity, and is further required to have high speed and low power consumption.
The NAND type flash memory has a memory array configured to have a plurality of blocks, the block is formed by configuring a plurality of NAND strings in column direction. The NAND string is formed by a plurality of memory cells connected in series and select transistors connected to two ends of the series, wherein one end is connected to the bit line via a bit line side select transistor, and another end is connected to the source line via a source line side select transistor.
FIG. 1 is as diagram indicating a structure of a bit line select circuit of a conventional flash memory (Patent document 1). As shown in FIG. 1, a bit line select circuit 10 includes a first select element 12 and a second select element 14, the first select element 12 is configured to connect an even-numbered bit line GBL_e and an odd-numbered bit line GBL_o to a page buffer/sense circuit, the second select element 14 applies a specified bias voltage to the even-numbered bit line GBL_e and the odd-numbered bit line GBL_o. The first select element 12 has an even-numbered select transistor SEL_e connected to the even-numbered bit line GBL_e, an odd-numbered select transistor SEL_o connected to the odd-numbered bit line GBL_o, and a bit line select transistor BLS connected between the sense circuit and a common node N1 of the even-numbered bit line GBL_e and the odd-numbered bit line GBL_o. The transistors SEL_e, SEL_o, and BLS forming the first select element 12 are N channel metal oxide semiconductor transistors formed in P-wells of peripheral circuits forming the page buffer/sense circuit, these transistors are high voltage transistors that are able to operate in a high voltage condition.
For example, when the read-out operation of the page is executed and the even-numbered bit line GBL_e is selected, the even-numbered select transistor SEL_e and the bit line select transistor BLS are turned on, the odd-numbered bit line GBL_o is non-selected, and the odd-numbered select transistor SEL_o is turned off. In addition, when the odd-numbered bit line GBL_o is selected, the odd-numbered select transistor SEL_o and the bit line select transistor BLS are turned on, the even-numbered bit line GBL_e is non-selected, and the even-numbered select transistor SEL_e is turned off.
The second select element 14 has an even-numbered bias transistor YSEL_e connected between the even-numbered bit line GBL_e and an imaginary electric potential VPRE, and an odd-numbered bias transistor YSEL_o connected between the odd-numbered bit line GBL_o and the imaginary electric potential VPRE. These transistors are NMOS transistors formed in P-wells having memory cells and are low voltage transistors that are able to operate in a low voltage condition. A bias voltage corresponding to operate condition or a precharge voltage are provided to the imaginary electric potential VPRE. For example, when the read-out operation of the page is executed, the even-numbered bias transistor YSEL_e of the selected even-numbered bit line GBL_e is turned off, the odd-numbered bias transistor YSEL_o of the non-selected odd-numbered bit line GBL_o is turned on, and a mask voltage is provided to the imaginary electric potential VPRE. In addition, when the even-numbered bit line GBL_e is non-selected and the odd-numbered bit line GBL_o is selected, the even-numbered bias transistor YSEL_e is turned on, the odd-numbered bias transistor YSEL_o is turned off, and the mask voltage is provided to the even-numbered bit line GBL_e. When the program operation is executed, a program inhibit voltage is provided to the imaginary electric potential VPRE, a write inhibit voltage is provided to the channel of the memory cell of the non-selected bit line. Via the transistors of the second select element 14 being formed in the well shared by the memory cells, the area occupied by the bit line select transistors may be reduced to compact the flash memory.
In the future, along with the popularity of internet devices, power consumption of the electronic equipment will be restricted, and high-speed data communication between electronic equipments will be further desired. Consequently, the flash memory powered by the electronic equipment is also further required to have low power consumption, high speed, and miniaturization. The layout structure in the patent document 1 (Japan Patent Publication No. 5550609) is one solution, but this structure is an insufficient solution, and thus the flash memory needs being further improved.